In a power MOSFET, a source electrode and a gate electrode are normally laid out on one main surface of a semiconductor substrate, and a drain electrode is placed on the other main surface of the semiconductor substrate. The power MOSFET is packaged by joining the drain electrode to a die bond area of a lead frame. The die bond area of the lead frame forms a drain terminal, and the lead frame includes a source terminal and a gate terminal electrically isolated from the die bond area. The source electrode and gate electrode of the power MOSFET are connected to their corresponding source and gate terminals through slender metal wires. The source electrode is connected to the source terminal via a plurality of slender metal wires to reduce on resistance.
A semiconductor package having built therein a semiconductor chip containing vertical MOS transistor is shown in FIG. 17 of Japanese Patent Laid-open No. 2002-359332. In the semiconductor package, metal electrodes lying on the chip are connected to their corresponding leads via a plurality of Au wires to reduce the wiring resistances of wires. In this case, the present publication describes that as the number of electrode pads increases and the connected number of Au wires increases, the number of indexes in an assembly process increases, and a further reduction in wiring resistance becomes difficult due to the wire lengths.
Further, FIG. 1 of Japanese Patent Laid-open No. 2002-359332 shows a structure wherein conductive strip leads are joined to bump contacts on a semiconductor chip. Since the leads constituted of the conductive strips are directly joined to the bump contacts, the wiring resistance can be reduced as compared with one that uses slender metal wires.
In the structure shown in FIG. 1 of Japanese Patent Laid-open No. 2002-359332, however, the two leads comprising the conductive strips are disposed on the semiconductor chip. Further, there is a need to mount these leads to the semiconductor chip respectively upon assembly.